TIMOUT=one, TIMDEC=flexio_clk_shiftclk_tmr_out, TIMRST=never, TIMENA=enable, TSTART=disable, TSTOP=stop_disable, TIMDIS=never
Timer Configuration N Register
| TSTART | Timer Start Bit 0 (disable): Start bit disabled 1 (enable): Start bit enabled |
| TSTOP | Timer Stop Bit 0 (stop_disable): Stop bit disabled 1 (enable_tmrcmp): Stop bit is enabled on timer compare 2 (enable_tmrdisable): Stop bit is enabled on timer disable 3 (enable_tmr_cmp_dis): Stop bit is enabled on timer compare and timer disable |
| TIMENA | Timer Enable 0 (enable): Timer always enabled 1 (tmr_nminus1_en): Timer enabled on Timer N-1 enable 2 (tmr_trighi_en): Timer enabled on Trigger high 3 (tmr_trig_pin_hi_en): Timer enabled on Trigger high and Pin high 4 (tmr_pinrise_en): Timer enabled on Pin rising edge 5 (tmr_pinrise_trighi_en): Timer enabled on Pin rising edge and Trigger high 6 (tmr_trigrise_en): Timer enabled on Trigger rising edge 7 (tmr_trigedge_en): Timer enabled on Trigger rising or falling edge |
| TIMDIS | Timer Disable 0 (never): Timer never disabled 1 (tmr_nminus1): Timer disabled on Timer N-1 disable 2 (tmr_cmp): Timer disabled on Timer compare (upper 8-bits match and decrement) 3 (tmr_cmp_triglow): Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 4 (pin_edge): Timer disabled on Pin rising or falling edge 5 (pin_edge_trighi): Timer disabled on Pin rising or falling edge provided Trigger is high 6 (trig_falledge): Timer disabled on Trigger falling edge |
| TIMRST | Timer Reset 0 (never): Timer never reset 2 (pin_eq_tmr_out): Timer reset on Timer Pin equal to Timer Output 3 (trig_eq_tmr_out): Timer reset on Timer Trigger equal to Timer Output 4 (pin_rise_edge): Timer reset on Timer Pin rising edge 6 (trig_rise_edge): Timer reset on Trigger rising edge 7 (trig_edge): Timer reset on Trigger rising or falling edge |
| TIMDEC | Timer Decrement 0 (flexio_clk_shiftclk_tmr_out): Decrement counter on FlexIO clock, Shift clock equals Timer output. 1 (trig_edge_shiftclk_tmr_out): Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 2 (pin_edge_shiftclk_tmr_out): Decrement counter on Pin input (both edges), Shift clock equals Pin input. 3 (trig_edge_shiftclk_trig_in): Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. |
| TIMOUT | Timer Output 0 (one): Timer output is logic one when enabled and is not affected by timer reset 1 (zero): Timer output is logic zero when enabled and is not affected by timer reset 2 (one_tmrreset): Timer output is logic one when enabled and on timer reset 3 (zero_tmrreset): Timer output is logic zero when enabled and on timer reset |